1. Field of the Invention
The present invention is directed to a logic circuit synthesizer for synthesizing a logic circuit which is excellent in both electrical characteristics and a dimensional accuracy.
2. Description of the Prior Art
A conventional logic circuit synthesizer levels and thereafter synthesizes an established logic circuit into a new logic circuit with further optimized features without changing the logics of the logic circuit.
FIG. 1 is a circuitry diagram of an object logic circuit which is to be synthesized into an optimized new logic circuit by a conventional logic circuit synthesizer. In FIG. 1, a composite gate 51 and a flip-flop 52, which are logic function blocks, form a logic function block 55, and a parallel arrangement of the logic function blocks 55 form a larger logic function block 50. Indicated at reference character RST is a reset signal and indicated at reference character CKT is a clock signal.
As herein termed, "logic primitive" refers to a simple clement such as an AND gate and an OR gate while "logic function block" refers to an advanced logic block which is comprised of logic primitives as combined each other and which therefore features an advanced logic function. If logic function blocks are combined together, an even more advanced logic function block is realized.
Assume that the logic circuit of FIG. 1 is inputted to the conventional logic circuit synthesizer. The logic of each one of partitioned logic function blocks is expressed as a conjunctive canonical form according to the Boolean expression. For example, the logic function block 55 of FIG. 1 is divided into two logic function blocks, i.e., the composite gate 51 and the flip-flop 52, and the composite gate 51 and the flip-flop 52 are each expressed as conjunctive canonical form.
The conjunctive canonical forms are expanded so that the logic circuit as a whole is expressed as a conjunctive canonical form. Following this, according to the distributive law, parenthesis grouping a plurality of logics are removed to thereby express the functions of the LSI as a principal conjunctive canonical form. The principal conjunctive canonical form is simplified by known logical mathematical process, thus completing leveling of the logic circuit. In general, the leveling is continued until the logics of the logic circuit are simplified to logical primitive level.
Upon the leveling, the logical formulas are translated in light of technical rules and restraints which are prescribed in a technology library, concurrently with which terms of the logical formulas are combined in the same manner in which an ordinary formula is factorized, so that restraint-considered logical formulas are newly synthesized.
Thus, the conventional logic circuit synthesizer constituted as above levels and thereafter synthesizes a logic circuit which is received therein.
The leveling in the conventional logic circuit synthesizer does not consider the constitution of each logic function block. For instance, as a result of the leveling by the logic circuit of FIG. 1, the composite gate 51 and the flip-flop 52, which are to be enclosed in the logic function block 55, are expanded as completely irrelevant logic function blocks as shown in FIG. 2.
Hence, there is no guarantee that the composite gate 51 and the flip-flop 52 are synthesized into the logic function block 55 again. Rather, there is a strong possibility of failed synthesizing. In a likely event that the original logic function block 55 is not restored, a synthesized logic circuit is inferior to the original logic circuit in terms of electrical characteristics and a dimensional accuracy (e.g., lingered delay times, an increased space occupied by the circuit and longer wire lengths).